This invention relates to a logic simulation method and apparatus used for verifying the operation of a logic circuit and more particularly to an event driven type logic simulation method and apparatus.
In the event driven type logic simulation, the change in status of a signal in a logic circuit to be simulated is deemed as an occurrence of an event and a series of signal status changes is handled as a series of events. Data representative of an event contains "event time" data indicative of the time that the signal status changes, "post-status" data indicative of a signal status after a change and "additional information" data indicative of a logic element number in which the signal status changes.
Also, in the event driven type simulation, only a logic element which experiences a signal status change at its input terminal is considered such that a signal status at its output terminal is calculated. When calculation results of calculation indicate that the signal status at the output terminal changes, an event to this effect is newly created and transmitted to an input terminal of a succeeding logic element connected to the output terminal of the preceding logic element. If calculation results indicate that the signal status at the output terminal does not change, no new event is created.
The event driven type logic simulation is executed by repeating three processes which include a process for evaluating an event representative of a signal status change at an input terminal of a logic element and calculating events representative of signal status changes at an output terminal of the logic element ("evaluation process"), a process for deciding/extracting an event deserving evaluation from a group of events calculated in the evaluation process ("take-out process") and a process for transmitting an event representative of a signal status change at the output terminal of the logic element to an input terminal of a succeeding logic element connected to the output terminal of the preceding logic element ("transmission process").
In deciding an event deserving evaluation, a method as described in "Design II of VLSI", Iwanami Lectureship, Microelectronics, pp. 191-210 is employed wherein an event which has a minimum of values of event times of all events in the logic simulation apparatus and which represents a signal status change at the input terminal of a logic element is decided to deserve elevation. In other words, this method sequentially evaluates events, starting from an event having a smaller (earlier) event time, and calculates a signal status at the output of a logic element relating to an evaluated event.
Recently, in order to speed up simulation, a system is provided wherein a processor is managed to carry out the take out process, evaluation process and transmission process through pipeline processing or a plurality of processors for pipeline processing are grouped in a logic simulation processor unit and the logic simulation processors are arranged in parallel and operated for parallel processings.
Typically, in the simulation apparatus, a current time output unit for indicating the current time is provided, an event having an event time coincident with the current time is decided to deserve elevation, and the current time is incremented by one when the event relating to the current time disappears in the logic simulation processor.
Updating of the current time must be done in such a manner that updated current time should not exceed not only event time of an event generated through the take-out process, evaluation process and transmission process but also event time of an event or "injection event" representative of a signal status change which is externally applied to the logic circuit to be simulated.
Accordingly, in the prior art logic simulation apparatus, all injection events are stored in an event storage unit of the logic simulation processor in advance of execution of the simulation or the simulation is temporarily stopped each time that current time is advanced to some extent, injection events each having an event time which is slightly greater than the current time are injected into the logic simulation processor and after completion of storage by the logic simulation processor of all the injection events in the event storage unit, the simulation is restarted.
The prior art logic simulation method and apparatus however face the following problems.
More particularly, in the prior art logic simulation method and apparatus in which all of the injection events are stored in the event storage unit in advance of execution of the simulation, there arises a problem in that memory capacity of the event storage unit is consumed greatly by the injection events.
Secondly, in the prior art logic simulation method and apparatus in which the simulation is temporarily stopped each time that a current time is advanced to some extent, injection events each having an event time which is slightly greater than the current time are injected into the logic simulation processor and after completion of storage of all the injection events in the event storage unit of the logic simulation processor, the simulation is restarted, there arises a problem in that simulation speed is degraded.